1. Field of the Invention
The present invention relates to a multichannel receiver circuit that suppresses effectively crosstalk (signal interference) between the channels. More particularly, the invention relates to a multichannel receiver circuit for receiving in parallel electrical input signals to produce electrical output signals by way of respective channels, in which each of the output signals has two different logic levels, such as logic high (H) and low (L) levels, according to the level of a corresponding one of the input signals.
2. Description of the Related Art
In recent years, with the development and advance of communications technology, there is the growing need to transmit data at a possibly high speed not only in trunk lines but also in or between communication devices (e.g., transmission terminals and exchanges), or computers. In the high-speed transmission systems of this type, the xe2x80x9cparallel transmissionxe2x80x9d technique has been used, in which a high-speed signal is divided into rather low-speed signals and then, they are transmitted in parallel by way of multiple channels. xe2x80x9cMultichannel receiver circuitsxe2x80x9d are used for receiving and amplifying these rather low-speed signals in parallel through multiple channels.
With the multichannel receiver circuits of this type, an electric input signal with a relatively small amplitude is typically amplified by a built-in amplifier circuit to thereby produce an electric output signal with a relatively large amplitude in each channel. In this case, usually, the amplification factor of the amplifier circuit is considerably large.
FIG. 1 schematically shows the configuration of an example of the prior-art multichannel receiver circuits of this type. The receiver circuit 101 in FIG. 1 is formed and integrated on a semiconductor substrate 101a in the form of an Integrated Circuit (IC). The receiver circuit 101 comprises first to n-th sections with the same circuit configuration that constitute respectively the first to n-th channels, where n is an integer greater than unity.
In the first section for the first channel, an amplifier circuit 111-1 and an output buffer circuit 112-1 are provided. The amplifier circuit 111-1 receives a first input signal SIN1 through the first input terminal of the receiver circuit 101 and produces a first amplified input signal SINA1. The output buffer circuit 112-1 receives the first amplified input signal SINA1 from the circuit 111-1 and produces a first output signal SOUT1 at the first output terminal of the circuit 101.
In the second section for the second channel, an amplifier circuit 111-2 and an output buffer circuit 112-2 are provided. The amplifier circuit 112-2 receives a second input signal SIN2 through the second input terminal of the receiver circuit 101 and produces a second amplified input signal SINA2. The output buffer circuit 112-2 receives the second amplified input signal SINA2 from the circuit 111-2 and produces a second output signal SOUT2 through the second output terminal of the circuit 101.
Similarly, in the n-th section for the n-th channel, an amplifier circuit 111-n and an output buffer circuit 112-n are provided. The amplifier circuit 111-n receives a n-th input signal SINn through the n-th input terminal of the receiver circuit 101 and produces a n-th amplified input signal SINAn. The output buffer circuit 112-n receives the n-th amplified input signal SINAn from the circuit 111-n and produces a n-th output signal SOUTn at the n-th output terminal of the circuit 101.
Although not shown in FIG. 1 and described here, each of the third to (n-1)-th sections for the third to (n-1)-th channels has the same configuration and operation as the first, second, and n-th sections.
With the prior-art multichannel receiver circuit 101 shown in FIG. 1, the first to n-th sections for the first to n-th channels are formed and integrated on the semiconductor substrate 101a in the form of an IC. Thus, there is a disadvantage that a signal transmitted through one of the first to n-th channels is likely to be affected by another transmitted through an adjoining one or ones of these channels.
On the other hand, all of the first to n-th channels are not always used, in other words, there is a possibility that one or more channels is/are kept unused. Moreover, input of at least one of the first to n-th input signals may be stopped due to some fault such as transmission line disconnection. In these cases, the output signal of an unused channel or a channel having no input signal application is undefined (i.e., the channel in question is in the xe2x80x9cdon""t carexe2x80x9d state) and as a result, the said channel will enter its oscillation state that causes a noise with a large amplitude.
For example, as shown in FIG. 2, it is supposed that input of the first input signal SIN1 for the first channel is suddenly stopped at the time to due to line disconnection while the second to n-th input signal SIN2 to SINn for the rest of the channels are being inputted. In this case, the level of the first input signal is zero and thus, the first output signal SOUT1 enters its oscillation state and generates a pulsed noise in the first channel. The noise thus generated in the first channel tends to affect the nearest second input signal SIN2 by way of the substrate 101a or the IC package (not shown) at and after the disconnection time to. Thus, at and after the time to, there is a possibility that the second input signal SIN2 includes a pulsed noise with a large amplitude. If so, the second output signal SOUT2 includes a pulsed noise due to the noise of the second input signal SIN2, which degrades the signal to noise ratio (S/N) of the signal SOUT2 in the second channel.
There is a possibility that some of the third to n-th output signals SOUT3 to SOUTn include a pulsed noise due to the noise induced in the first channel.
Conventionally, since electric signals transmitted in parallel through multiple channels in the multichannel receiver circuit of this type have narrow bandwidths, the above-described disadvantage has occurred scarcely. In recent years, however, these receiver circuits have been highly integrated on a semiconductor substrate monolithically and at the same time, the signal speed for each channel has increased further. As a result, the above-described disadvantage of S/N degradation due to crosstalk has been becoming conspicuous.
With the prior-art multichannel receiver circuit 101 of FIG. 1, when one of the input signals SIN1 to SINn of the first to n-th channels does not exist due to some cause, the said input signal enters its oscillation state and then, a pulsed noise with large amplitude is generated therein. The pulsed noise thus produced tends to affect the input side of the adjoining channel or channels (i.e., crosstalk occurs) by way of the substrate 101a or the IC package. Thus, a pulsed noise occurs in the input signal for the adjoining channel. This means that not only the input signal of the adjoining channel but also the noise thereof are amplified and outputted as the output signal SOUT1 to SOUTn, resulting in S/N degradation due to crosstalk. This event becomes more conspicuous and serious as the signal speed increases.
Accordingly, an object of the present invention is to provide a multichannel receiver circuit that suppresses effectively crosstalk or interference between the electric signals transmitted in parallel through multiple channels at high speed.
Another object of the present invention is to provide a multichannel receiver circuit that prevents the generation of oscillation state for each channel.
Still another object of the present invention is to provide a multichannel receiver circuit that improves the S/N for each channel.
The above objects together with others not specifically mentioned will become clear to those skilled in the art from the following description.
A multichannel receiver circuit according to the invention comprises:
first to n-th sections for forming respectively first to n-th channels, where n is an integer greater than unity;
the first to n-th sections receiving first to n-th electric input signals to produce first to n-th electric output signals, respectively, where each of the first to n-th output signals having different logic levels according to a corresponding one of the first to n-th input signals;
each of the first to n-th sections including an output level fixer circuit that produces an output signal;
the output signal of the output level fixer circuit having a fixed level that induces no oscillation when a corresponding one of the first to n-th input signals has a level less than a specific reference level; and
the output signal of the output level fixer circuit having substantially a same waveform as that of a corresponding one of the first to n-th input signals when a corresponding one of the first to n-th input signals has a level equal to or greater than the specific reference level.
With the multichannel receiver circuit according to the invention, each of the first to n-th sections for forming respectively the first to n-th channels includes the level fixer circuit. The output signal of the output level fixer circuit has substantially a same waveform as that of a corresponding one of the first to n-th input signals when a corresponding one of the first to n-th input signals has a level equal to or greater than the specific reference level. Therefore, in this state, the function of the level fixer circuit is to pass a corresponding one of the first to n-th input signals through itself without substantially changing its waveform.
On the other hand, the output signal of the level fixer circuit has a fixed level that induces no oscillation when a corresponding one of the first to n-th input signals has a level less than the specific reference level. Therefore, even if one of the first to n-th channels is subjected to disappear of its input signal due to nonuse or line disconnection or the like and then, a corresponding one of the first to n-th input signals has a level less than the specific reference level, no oscillation occurs in the said channel. In other words, the channel is not turned into an undefined state, or it does not enter the xe2x80x9cdon""t carexe2x80x9d state, because of the operation of the level fixer circuit.
Accordingly, no crosstalk or interference occurs between adjoining ones of the first to n-th channels, which improves the S/N of the signal for each channel.
In a preferred embodiment of the circuit according to the invention, each of the first to n-th sections includes an amplifier circuit located prior to the level fixer circuit. An amplified input signal of the amplifier circuit is inputted into the level fixer circuit of a corresponding one of the first to n-th sections. In this embodiment, there is an additional advantage that the advantages of the invention are more conspicuous.
In another preferred embodiment of the circuit according to the invention, the level fixer circuit has an input-output characteristic with a hysteresis. Preferably, the hysteresis has a changeable width.
In this embodiment, preferably, the fixed level of the output signal of the level fixer circuit is equal to a logic L level or a logic H level. Alternately, the level-fixed output signal produced by the output level fixer circuit may be equal to an intermediate level between the logic L level and the logic H level.
In still another preferred embodiment of the circuit according to the invention, if the output signal of the level fixer circuit is in a logic L level at a time when a corresponding one of the first to n-th input signals has a level less than a specific reference level, the fixed level of the output signal of the level fixer circuit is equal to the logic L level. If the output signal of the level fixer circuit is in a logic H level at the said time, the fixed level of the output signal of the level fixer circuit is equal to the logic H level.
In a further preferred embodiment of the circuit according to the invention, the level fixer circuit is formed by a multilevel retainer circuit. The output signal of the multilevel retainer circuit has at least two different values for the logic L or H level. One of the at least two different values is selectively used.
In a still further preferred embodiment of the circuit according to the invention, the level fixer circuit is formed by a Schmitt trigger circuit.